View M38503M4H_128763.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec. H) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.
FEATURES
q Basic machine-language instructions ...................................... 71 q Minimum instruction execution time .................................. 0.5 s (at 8 MHz oscillation frequency) q Memory size ROM ................................................................... 8K to 32K bytes RAM ................................................................. 512 to 1024 bytes q Programmable input/output ports ............................................ 34 q Interrupts ................................................. 14 sources, 14 vectors q Timers ............................................................................. 8-bit ! 4 q Serial I/O1 .................... 8-bit ! 1(UART or Clock-synchronized) q Serial I/O2 ................................... 8-bit ! 1(Clock-synchronized) q PWM ............................................................................... 8-bit ! 1 q A-D converter ............................................... 10-bit ! 5 channels q Watchdog timer ............................................................ 16-bit ! 1 q Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator)
qPower source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) qPower dissipation In high-speed mode ..........................................................34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) qOperating temperature range .................................... -20 to 85C
APPLICATION
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK P25/TxD P24/RxD P23 P22 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7)
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38503M4H-XXXFP/SP pin configuration
M38503M4H-XXXFP M38503M4H-XXXSP
2
Reset input VSS VCC RESET
18 15 1 21
FUNCTIONAL BLOCK DIAGRAM
Main-clock input XIN CNVSS
Main-clock output XOUT
19
20
FUNCTIONAL BLOCK
Sub-clock Sub-clock input output
Fig. 2 Functional block diagram
CPU
XCIN
XCOUT
Clock generating circuit
RAM ROM
X
Prescaler 12(8)
A Timer 2( 8 ) Timer X( 8 ) Timer Y( 8 )
Timer 1( 8 )
Y
Prescaler X(8)
S PC H PS
CNTR1
PCL
Prescaler Y(8)
CNTR0
Watchdog timer
Reset
A-D converter (10)
PWM (8)
SI/O1(8)
XCOUT
SI/O2(8)
XCIN INT0- INT3
P4(5)
P3(5)
P2(8)
P1(8)
P0(8)
23 38 39 40 41 42
45 678
9 10 11 12 13 1416 17
22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37
I/O port P4 I/O port P3
I/O port P2
I/O port P1
I/O port P0
VREF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3850 Group (Spec. H)
MITSUBISHI MICROCOMPUTERS
AVSS
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description Pin VCC, VSS CNVSS RESET XIN XOUT P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04-P07 P10-P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK P27/CNTR0/ SRDY1 P30/AN0- P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM I/O port P4 *8-bit CMOS I/O port with the same function as port P0. I/O port P3 *CMOS compatible input level. *CMOS 3-state output structure. *8-bit CMOS I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure. * Interrupt input pin * SCMP2 output pin * Interrupt input pin * PWM output pin * Timer Y function pin * Interrupt input pins * Serial I/O1 function pin/ Timer X function pin * A-D converter input pin I/O port P2 Name Power source CNVSS input Reset input Clock input Clock output Functions *Apply voltage of 2.7 V - 5.5 V to Vcc, and 0 V to Vss. *This pin controls the operation mode of the chip. *Normally connected to VSS. *Reset input pin for active "L." *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *8-bit CMOS I/O port. I/O port P0 *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. I/O port P1 *P10 to P17 (8 bits) are enabled to output large current for LED drive. *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *P20, P21, P24 to P27: CMOS3-state output structure. *P22, P23: N-channel open-drain structure. * Serial I/O1 function pin * Sub-clock generating circuit I/O pins (connect a resonator) * Serial I/O2 function pin
Function except a port function
3
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product name
M3850 3
M
4
H- XXX
SP
Package type SP : 42P4B FP : 42P2R-A/E SS : 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. - : standard Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. H-: Partial specification changed version ROM/PROM/Flash memory size 9 : 36864 bytes 1 : 4096 bytes 2 : 8192 bytes A : 40960 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user's ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version E : EPROM or One Time PROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes
5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 3 Part numbering
4
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3850 group (spec. H) as follows.
Packages
42P4B ......................................... 42-pin shrink plastic-molded DIP 42P2R-A/E ........................................... 42-pin plastic-molded SOP 42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and flash memory versions.
Memory Size
Flash memory size ......................................................... 32 K bytes One Time PROM size ..................................................... 24 K bytes Mask ROM size ................................................... 8 K to 32 K bytes RAM size ............................................................... 512 to 1 K bytes
Memory Expansion Plan
ROM size (bytes) ROM exteranal 32K 28K
Mass production Under development
As of Feb. 2000
M38507M8/F8
24K 20K
M38504M6/E6
Mass production
16K 12K
M38503M4H
Mass production
8K
M38503M2H
384
512
640
768
1152 896 1024 RAM size (bytes)
1280
1408
1536
2048
Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped.
Fig. 4 Memory expansion plan
5
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Currently planning products are listed below. Table 2 Support products Product name M38503M2H-XXXSP M38503M2H-XXXFP M38503M4H-XXXSP M38503M4H-XXXFP M38504M6-XXXSP M38504E6-XXXSP M388504E6SP M388504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP ROM size (bytes) ROM size for User in ( ) 8192 (8062) 16384 (16254) RAM size (bytes) 512 512 Package 42P4B 42P2R-A/E 424P4B 42P2R-A/E 424P4B 24576 (24446) 640 42S1B-A 42P2R-A/E Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) As of Feb. 2000
Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products 3850 group (standard) 3850 group (spec. H) M38503M2-XXXFP/SP M38503M2H-XXXFP/SP M38503M4-XXXFP/SP M38503M4H-XXXFP/SP M38503E4-XXXFP/SP M38504M6-XXXFP/SP M38503E4FP/SP M38504E6-XXXFP/SP M38503E4SS M38504E6FP/SP M38504E6SS M38507M8-XXXFP/SP M38507F8FP/SP
Table 4 Differences between 3850 group (standard) and 3850 group (spec. H) Serial I/O A-D converter Large current port 3850 group (standard) 1: Serial I/O (UART or Clock-synchronized) Unserviceable in low-speed mode 5: P13-P17 3850 group (spec. H) 2: Serial I/O1 (UART or Clock-synchronized) Serial I/O2 (Clock-synchronized) Serviceable in low-speed mode 8: P10-P17
Notes on differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard). *Power source voltage Vcc = -0.3 to 6.5 V *CNVss input voltage VI = -0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to "1". (5) Be sure to perform the termination of unused pins.
6
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL
b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
NVTBD I ZC
Fig. 5 740 Family CPU register structure
7
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack
Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S)
I Flag is set from "0" to "1" Fetch the jump vector
POP contents of processor status register from stack
POP return address from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is "1" Interrupt disable flag is "0"
Fig. 6 Register push and pop at interrupt generation and subroutine call Table 5 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
8
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
*Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
9
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available
Fig. 7 Structure of CPU mode register
10
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size (bytes) Address XXXX16
000016 SFR area 004016 010016 Zero page
192 256 384 512 640 768 896 1024 1536 2048
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16
RAM
XXXX16 Not used 0FF016 0FFF16 SFR area (Note) Not used
ROM area
ROM size (bytes) Address YYYY16 Address ZZZZ16
YYYY16 Reserved ROM area
(128 bytes)
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ZZZZ16
ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page
Reserved ROM area
Note: Flash memory version only
Fig. 8 Memory map diagram
11
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS)
Reserved V Reserved V Reserved V Reserved V Reserved V Reserved V Reserved V
Reserved V Reserved V Reserved V Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM)
003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 A-D control register (ADCON) A-D conversion low-order register (ADL) A-D conversion high-order register (ADH) Reserved V MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
V Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
12
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 5 I/O port function Pin P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04-P07 P10-P17 P20/XCOUT P21/XCIN P22 P23 CMOS compatible input level N-channel open-drain output Input/output, individual bits Serial I/O1 function I/O Serial I/O1 control register Serial I/O1 control register Serial I/O1 control register Timer XY mode register A-D control register Timer XY mode register Interrupt edge selection register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register PWM control register Port P1 Sub-clock generating circuit CPU mode register Name Input/Output I/O Structure Non-Port Function Related SFRs Serial I/O2 control register Ref.No. (1) (2) (3) (4) (5) (6) (7) (8)
Serial I/O2 function I/O Port P0 CMOS compatible input level CMOS 3-state output
Port P2
P24/RxD P25/TxD P26/SCLK P27/CNTR0/SRDY1 P30/AN0- P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2
(9) (10) (11)
Serial I/O1 function I/O Serial I/O1 function I/O CMOS compatible input level CMOS 3-state output Port P3 Timer X function I/O A-D conversion input Timer Y function I/O External interrupt input Port P4 External interrupt input SCMP2 output External interrupt input PWM output
(12)
(13) (14) (15)
(16)
P44/INT3/PWM
(17)
13
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P00
Direction register
(2) Port P01
P01/SOUT2 P-channel output disable bit Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 input Serial I/O2 output
(3) Port P02 (4) Port P03
P02/SCLK2 P-channel output disable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Data bus Port latch SRDY2 output enable bit Direction register
Port latch
Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input
(5) Ports P04-P07,P1
Direction register
(6) Port P20
Port XC switch bit Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator Port P21
(7) Port P21
Port XC switch bit Direction register Direction register
Port XC switch bit
(8) Ports P22,P23
Data bus
Port latch Data bus
Port latch
Sub-clock generating circuit input
Fig. 10 Port block diagram (1)
14
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P24
Serial I/O1 enable bit Receive enable bit Direction register Port latch
(10) Port P25
P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register
Data bus
Data bus
Port latch
Serial I/O1 input Serial I/O1 output
(11) Port P26
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch
(12) Port P27
Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Port latch
Pulse output mode Serial I/O1 clock output External clock input Serial ready output Timer output CNTR0 interrupt input
(13) Ports P30-P34
(14) Port P40
Direction register Direction register
Data bus Data bus Port latch
Port latch
A-D converter input Analog input pin selection bit
Pulse output mode Timer output CNTR1 interrupt input
(16) Port P43 (15) Ports P41,P42
Direction register Serial I/O2 I/O comparison signal control bit Direction register
Data bus
Port latch
Data bus
Port latch
Interrupt input
Serial I/O2 I/O comparison signal output Interrupt input
Fig. 11 Port block diagram (2)
15
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port P44
PWM output enable bit Direction register
Data bus
Port latch
PWM output Interrupt input
Fig. 12 Port block diagram (3)
16
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software.
sNotes
When the active edge of an external interrupt (INT0-INT3, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: 1. Disable the interrupt 2. Change the interrupt edge selection register (the timer XY mode register for CNTR0 and CNTR1) 3. Clear the interrupt request bit to "0" 4. Accept the interrupt.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
17
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 Reserved INT1 INT2 INT3/ Serial I/O2 Priority 1 2 3 4 5 6 Vector Addresses (Note 1) Low High FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFFA16 FFF816 FFF616 FFF416 FFF216 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input Reserved At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input/ At completion of serial I/O2 data reception/transmission Reserved At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion At BRK instruction execution Non-maskable software interrupt Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Switch by Serial I/O2/INT3 interrupt source bit Remarks Non-maskable External interrupt (active edge selectable)
Reserved Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception Serial I/O1 transmission CNTR0 CNTR1 A-D converter BRK instruction
7 8 9 10 11 12
FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716
FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616
STP release timer underflow
13
FFE516
FFE416
14 15 16 17
FFE316 FFE116 FFDF16 FFDD16
FFE216 FFE016 FFDE16 FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
18
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit 0 : Falling edge active 1 : Rising edge active INT2 active edge selection bit INT3 active edge selection bit Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns "0" when read)
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit Reserved(Do not write "1" to this bit.) INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit Reserved(Do not write "1" to this bit.) Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
19
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3850 group (spec. H) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1".
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source selection bit.
b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is "0", the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is "1", the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge selection bit is "1", the timer counts it while the CNTR0 (or CNTR1) pin is at "L". The count can be stopped by setting "1" to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.
Fig. 15 Structure of timer XY mode register
b7
b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns "0" when read)
sNote
When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer.
Fig. 16 Structure of timer count source selection register
20
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 Pulse width (f(XCIN)/2 at low-speed mode) Timer X count source selection bit measurement mode CNTR0 active edge selection "0" bit "1"
Prescaler X latch (8) Timer mode Pulse output mode Prescaler X (8) Event counter mode Timer X count stop bit
Timer X latch (8)
Timer X (8)
To timer X interrupt request bit
P27/CNTR0
To CNTR0 interrupt request bit
CNTR0 active edge selection "1" bit "0"
Q Q
Toggle flip-flop T R Timer X latch write pulse Pulse output mode
Port P27 direction register
Port P27 latch Pulse output mode Data bus
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit CNTR1 active edge selection bit "0" "1" Pulse width measurement mode
Prescaler Y latch (8) Timer mode Pulse output mode Prescaler Y (8)
Timer Y latch (8)
Timer Y (8)
To timer Y interrupt request bit
P40/CNTR1
Event counter mode
Timer Y count stop bit To CNTR1 interrupt request bit
CNTR1 active edge selection "1" bit "0"
Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode
Port P40 direction register
Port P40 latch
Pulse output mode Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XCIN) Timer 12 count source selection bit
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit To timer 1 interrupt request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
21
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Data bus Address 001816 Receive buffer register P24/RXD Receive shift register Shift clock Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
P26/SCLK Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 Clock control circuit Shift clock P25/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
XIN
BRG count source selection bit 1/4
P27/SRDY1
F/F
Falling-edge detector
Fig. 18 Block diagram of clock synchronous serial I/O1
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 19 Operation of clock synchronous serial I/O1 function
22
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE SP detector Clock control circuit Serial I/O synchronous clock selection bit P26/SCLK BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) UART control register Address 001B16
P24/RXD
Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register 8 bits
XIN
Fig. 20 Block diagram of UART serial I/O1
23
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST TBE=0 TBE=1 TSC=1
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
24
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins)
b7
b0
UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
Fig. 22 Structure of serial I/O1 control registers
25
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when SCLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16).
b7 b0
Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits
b2 b1 b0
0 0 0 0 1 1
0 0 1 1 1 1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin
SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode )
b7 b0
Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits
b2 b1 b0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: 1 bit 1: 2 bit 0: 3 bit 1: 4 bit 0: 5 bit 1: 6 bit 0: 7 bit 1: 8 bit
Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance
Fig. 23 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 23.
26
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1/8
XCIN
Divider Main clock division ratio selection bits (Note) "10" "00" "01"
Internal synchronous clock selection bit
1/16 1/32 1/64 1/128 1/256
Data bus
XIN
P03 latch
"0" Serial I/O2 synchronous clock selection bit
P03/SRDY2
"1" "0"
SCLK2
SRDY2 Synchronous circuit "1" SRDY2 output enable bit External clock
P02 latch
"0"
Optional transfer bits (3) Serial I/O counter 2 (3) Serial I/O2 interrupt request
P02/SCLK2
"1" Serial I/O2 port selection bit
P01 latch
"0"
P01/SOUT2
"1" Serial I/O2 port selection bit
P00/SIN2
Serial I/O2 register (8)
P43 latch
"0"
P43/SCMP2/INT2
"1" Serial I/O2 I/O comparison signal control bit
D Q
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 24 Block diagram of Serial I/O2
Transfer clock (Note 1) Write-in signal to serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2 Serial I/O2 input SIN2
D0
D1
.
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 25 Timing chart of Serial I/O2
27
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SCMP2 SCLK2 SOUT2 SIN2
Judgement of I/O data comparison
Fig. 26 SCMP2 output operation
28
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 3850 group (spec. H) has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
Data Setting
The PWM output pin also functions as port P44. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ! (n+1) / f(XIN) = 31.875 ! (n+1) s (when f(XIN) = 8 MHz,count source selection bit = "0") Output pulse "H" term = PWM period ! m / 255 = 0.125 ! (n+1) ! m s (when f(XIN) = 8 MHz,count source selection bit = "0")
31.875 ! m ! (n+1) s 255 PWM output T = [31.875 ! (n+1)] s m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X IN) = 8 MHz,count source selection bit = "0")
Fig. 27 Timing of PWM period
Data bus
PWM prescaler pre-latch
PWM register pre-latch
Transfer control circuit
PWM prescaler latch Count source selection bit XIN (XCIN at low-speed mode) 1/2 "0" "1" PWM prescaler
PWM register latch
Port P44 PWM register
Port P44 latch
PWM enable bit
Fig. 28 Block diagram of PWM function
29
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) (f(XCIN) at low-speed mode) 1: f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return "0" when read)
Fig. 29 Structure of PWM control register
A PWM output T PWM register write signal
B
C
B= C T2 T
T (Changes "H" term from "A" to "B".)
T2
PWM prescaler write signal
(Changes PWM period from "T" to "T2".)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 30 PWM output timing when PWM register or PWM prescaler is changed
sNote
The PWM starts after the PWM function enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows:
n+1 2 * f(XIN) n+1 f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
30
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616
The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion.
b7
b0
AD control register (ADCON : address 003416) Analog input pin selection bits
b2 b1 b0
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion.
0 0 0 0 1
0 0 1 1 0
0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4
Not used (returns "0" when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns "0" when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Fig. 31 Structure of AD control register
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator.
10-bit reading (Read address 003616 before 003516)
b7
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(XIN) and f(XCIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit.
(Address 003616)
b7
b0 b9 b8 b0
(Address 003516) b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 0036 16 become "0" at reading.
8-bit reading (Read only address 003516)
b7 b0
(Address 003516) b9 b8 b7 b6 b5 b4 b3 b2
Fig. 32 Structure of A-D conversion registers
Data bus
AD control register (Address 0034 16)
b7
b0
3 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 A-D control circuit A-D interrupt request
Channel selector
Comparator
A-D conversion high-order register (Address 0036 16) A-D conversion low-order register (Address 0035 16) 10 Resistor ladder
VREF AVSS
Fig. 33 Block diagram of A-D converter
31
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 003916) may be started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. qInitial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to "FF16."
qWatchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 s at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to "0" after reset. qOperation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after reset.
XCIN "10" Main clock division ratio selection bits (Note) XIN
"FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/16 "00" "01" "1" Watchdog timer H (8)
Data bus "FF16" is set when watchdog timer control register is written to.
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 34 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16
Fig. 35 Structure of Watchdog timer control register
32
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC Power source voltage detection circuit
Fig. 36 Reset circuit example
XIN
RESET
RESETOUT
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN) = 2 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals.
Fig. 37 Reset sequence
33
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 001516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) MISRG (35) Watchdog timer control register (WDTCON) (36) Interrupt edge selection register (INTEDGE) (37) CPU mode register (CPUM) (38) Interrupt request register 1 (IREQ1) (39) Interrupt request register 2 (IREQ2) (40) Interrupt control register 1 (ICON1) (41) Interrupt control register 2 (ICON2) (42) Processor status register (43) Program counter
Address Register contents 003816 0016
003916 0 0 1 1 1 1 1 1 003A16 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) 0016 0016 0016 0016 XXXXX1XX
FFFD16 contents FFFC16 contents
(10) Port P4 direction register (P4D) (11) Serial I/O2 control register 1 (SIO2CON1) (12) Serial I/O2 control register 2 (SIO2CON2) (13) Serial I/O2 register (SIO2) (14) Transmit/Receive buffer register (TB/RB) (15) Serial I/O1 status register (SIOSTS) (16) Serial I/O1 control register (SIOCON) (17) UART control register (UARTCON) (18) Baud rate generator (BRG) (19) PWM control register (PWMCON) (20) PWM prescaler (PREPWM) (21) PWM register (PWM) (22) Prescaler 12 (PRE12) (23) Timer 1 (T1) (24) Timer 2 (T2) (25) Timer XY mode register (TM) (26) Prescaler X (PREX) (27) Timer X (TX) (28) Prescaler Y (PREY) (29) Timer Y (TY) (30) Timer count source selection register (TCSS) (31) A-D control register (ADCON) (32) A-D conversion low-order register (ADL) (33) A-D conversion high-order register (ADH)
001616 0 0 0 0 0 1 1 1 001716 X X X X X X X X 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016
001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016
001E16 X X X X X X X X 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 002816 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016
003416 0 0 0 1 0 0 0 0 003516 X X X X X X X X 003616 0 0 0 0 0 0 X X
Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 38 Internal status at reset
34
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3850 group (spec. H) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
(2) Wait mode
If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to "1" before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to "0" before executing the STP instruction.
Frequency Control (1) Middle-speed mode
The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected.
sNote (2) High-speed mode
The internal clock is half the frequency of XIN. When using the oscillation stabilizing time set after STP instruction released bit set to "1", evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
(3) Low-speed mode
The internal clock is half the frequency of XCIN.
sNote
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3*f(XCIN).
XCIN Rf CCIN XCOUT Rd CCOUT CIN COUT XIN XOUT
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Fig. 39 Ceramic resonator circuit
XCIN
XCOUT Rd CCOUT
XIN
XOUT Open
Oscillation Control (1) Stop mode
If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is "0," the prescaler 12 is set to "FF16" and timer 1 is set to "0116." When the oscillation stabilizing time set after STP instruction released bit is "1," set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either XIN or XCIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated.
Rf CCIN
External oscillation circuit Vcc Vss
Fig. 40 External clock input circuit
35
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[MISRG (MISRG)] 003816
MISRG consists of three control bits (bits 1 to 3) for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic switch start bit to "1" while operating in the low-speed mode and setting the middlespeed mode automatic switch set bit to "1", XIN oscillation automatically starts and the mode is automatically switched to the middle-speed mode.
b7
b0
MISRG (MISRG : address 003816) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return "0" when read) Note: When the mode is automatically switched from the low-speed mode to the middle-speed mode, the value of CPU mode register (address 003B16) changes.
Fig. 41 Structure of MISRG
XCIN
XCOUT
"1"
"0"
Port XC switch bit
XIN
XOUT
Main clock division ratio selection bits (Note 1) Low-speed mode
1/2
High-speed or middle-speed mode
1/4
1/2
Prescaler 12 FF16
Timer 1 0116
Reset or STP instruction (Note 2)
Main clock division ratio selection bits (Note 1) Middle-speed mode High-speed or low-speed mode Main clock stop bit
Timing f (internal clock)
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset Interrupt disable flag l Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b1) to "1". 2: When bit 0 of MISRG = "0"
Fig. 42 System clock generating circuit block diagram (Single-chip mode)
36
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (f() = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped)
CM6 "1" "0"
High-speed mode (f() = 4 MHz) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped)
" "0 4 M " C" "0 "1 M6 C " "1
C "0 M4 CM " "1 6 " "1 " "0 "
Middle-speed mode (f() = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating)
CM4 "1" "0"
CM6 "1" "0"
CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating)
Low-speed mode (f()=16 kHz) CM7 = 1 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating)
CM7 "1" "0"
C "0 M7 CM " "1 6 "1 " " "0 "
CM4 "1" "0"
High-speed mode (f() = 4 MHz)
b7
b4 CPU mode register (CPUM : address 003B16)
CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 ( High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available
Low-speed mode (f()=16 kHz) CM7 = 1 CM6 = 0 CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When bit 0 of MISRG is "0" and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : When bit 0 of MISRG is "0" and the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is "0". (2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is "1". 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f indicates the internal clock.
Fig. 43 State transitions of system clock
CM5 "1" "0"
37
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) in the middle/high-speed mode is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency in high-speed mode.
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
NOTES ON USAGE Differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard). *Power source voltage Vcc = -0.3 to 6.5 V *CNVss input voltage VI = -0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to "1". (5) Be sure to perform the termination of unused pins.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1F is recommended.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to "1." Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed. When an external clock is used as synchronous clock in serial I/ O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is "H."
38
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 7 Absolute maximum ratings Symbol VCC VI Parameter Power source voltage Input voltage P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44, VREF Input voltage Input voltage Input voltage Output voltage P22, P23 RESET, XIN CNVSS P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature All voltages are based on VSS. Output transistors are cut off. Conditions Ratings -0.3 to 6.5 -0.3 to VCC +0.3 -0.3 to 5.8 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 5.8 1000 (Note) -20 to 85 -40 to 125 Unit V V V V V V V mW C C
VI VI VI VO VO Pd Topr Tstg
Ta = 25 C
Note : The rating becomes 300mW at the 42P2R-A/E package.
Table 8 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Power source voltage Parameter 8 MHz (high-speed mode) 8 MHz (middle-speed mode), 4 MHz (high-speed mode) Min. 4.0 2.7 2.0 0 AN0-AN4 P00-P07, P10-P17, P20-P27, P30-P34, P40-P44 RESET, XIN, CNVSS P00-P07, P10-P17, P20-P27, P30-P34, P40-P44 RESET, CNVSS XIN P00-P07, P10-P17, P30-P34 (Note) P20, P21, P24-P27, P40-P44 (Note) P00-P07, P30-P34 P10-P17 P20-P27,P40-P44 (Note) P00-P07, P10-P17, P30-P34 (Note) P20, P21, P24-P27, P40-P44 (Note) P00-P07, P30-P34 P10-P17 P20-P27,P40-P44 (Note) AVSS 0.8VCC 0.8VCC 0 0 0 VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC -80 -80 80 120 80 -40 -40 40 60 40 Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage "H" input voltage "H" input voltage "L" input voltage "L" input voltage "L" input voltage "H" total peak output current "H" total peak output current "L" total peak output current (Note) "L" total peak output current (Note) "L" total peak output current "H" total average output current "H" total average output current "L" total average output current (Note) "L" total average output current (Note) "L" total average output current
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
39
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XIN) "H" peak output current Parameter P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 (Note 1) "L" peak output current (Note 1) P00-P07, P20-P27, P30-P34, P40-P44 "L" peak output current (Note 1) P10-P17 "H" average output current P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 (Note 2) "L" average output current (Note 2) P00-P07, P20-P27, P30-P34, P40-P44 "L" average output current (Note 2) P10-P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Min. Limits Typ. Max. -10 10 20 -5 5 15 8 4 Unit mA mA mA mA mA mA MHz MHz
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%.
40
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 10 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 (Note) "L" output voltage P00-P07, P20-P27, P30-P34, P40-P44 "L" output voltage P10-P17 Test conditions IOH = -10 mA VCC = 4.0-5.5 V IOH = -1.0 mA VCC = 2.7-5.5 V IOL = 10 mA VCC = 4.0-5.5 V IOL = 1.0 mA VCC = 2.7-5.5 V IOL = 20 mA VCC = 4.0-5.5 V IOL = 10 mA VCC = 2.7-5.5 V Min. VCC-2.0 VCC-1.0 2.0 1.0 2.0 1.0 0.4 0.5 0.5 VI = VCC 5.0 Typ. Max. Unit V V V V V V V V V A
VOL
VOL
VT+-VT- VT+-VT- VT+-VT- IIH
Hysteresis CNTR0, CNTR1, INT0-INT3 Hysteresis RxD, SCLK ____________ Hysteresis RESET "H" input current P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 ____________ "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27 P30-P34, P40-P44 ____________ "L" input current RESET,CNVSS "L" input current XIN RAM hold voltage
IIH IIH IIL
VI = VCC VI = VCC VI = VSS
5.0 4 -5.0
A A A
IIL IIL VRAM
VI = VSS VI = VSS When clock stopped
-5.0 -4 2.0 5.5
A A V
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0".
41
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter Test conditions High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors "off" Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C Min. Typ. 6.8 Max. 13 Unit
mA
1.6
mA
60
200
A
20
40
A
ICC
Power source current
20
55
A
5.0
10.0
A
4.0
7.0
mA
1.5
mA
800 0.1 1.0 10
A A A
42
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, f(XIN) = 8 MHz, unless otherwise noted) Symbol - - tCONV Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Test conditions Limits Min. Typ. Max. 10 4 61 Unit bit LSB 2tc(XIN) s k A A
High-speed mode, Middle-speed mode Low-speed mode VREF = 5.0 V 50
RLADDER IVREF II(AD)
Ladder resistor Reference power source input current A-D port input current
VREF "on" VREF "off"
40 35 150 0.5
200 5.0 5.0
43
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 13 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART).
Table 14 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 2 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is "0" (UART).
44
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Min. Typ. tC(SCLK1)/2-30 tC(SCLK1)/2-30 -30 30 30 tC(SCLK2)/2-160 tC(SCLK2)/2-160 200 0 10 10 30 30 30 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig.44
140
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is "0". 3: The XOUT pin is excluded.
Table 16 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Min. Typ. tC(SCLK1)/2-50 tC(SCLK1)/2-50 -30 50 50 tC(SCLK2)/2-240 tC(SCLK2)/2-240 400 0 20 20 50 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig.44
350
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is "0". 3: The XOUT pin is excluded.
45
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Measurement output pin 100pF
CMOS output
Fig. 44 Circuit for measuring output switching characteristics
46
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
CNTR0 CNTR1
tWH(CNTR) 0.8VCC 0.2VCC
tWL(CNTR)
tWH(INT)
tWL(INT) 0.2VCC
INT0 to INT3
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
SCLK1 SCLK2
tf
tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2VCC tsu(RxD-SCLK1), tsu(SIN2-SCLK2) 0.8VCC th(SCLK1-RxD), th(SCLK2-SIN2)
RXD SIN2
td(SCLK1-TXD), td(SCLK2-SOUT2)
0.8VCC 0.2VCC tv(SCLK1-TXD), tv(SCLK2-SOUT2)
TXD SOUT2
Fig. 45 Timing diagram
47
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
42P4B
EIAJ Package Code SDIP42-P-600-1.78 JEDEC Code - Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 600mil SDIP
42
22
1
21
Symbol
D
e SEATING PLANE
b1
b
b2
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Min Nom Max - - 5.5 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 - 1.778 - - 15.24 - 3.0 - - 0 - 15
A
42P2R-A/E
EIAJ Package Code SSOP42-P-450-0.80
42
A1
L
A2
Plastic 42pin 450mil SSOP
JEDEC Code - Weight(g) 0.63
22
Lead Material Alloy 42
e
e1
E
c
b2
HE
E
e1
F
Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - - 0.75 - - - 0.9 0.15 - - 0 - 10 - 0.5 - - 11.43 - - - 1.27
Symbol
1 21
A
G
D
A2 e y
b
A1
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
L1
c z Z1 Detail G Detail F
48
L
I2
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42S1B-A
EIAJ Package Code WDIP42-C-600-1.78 JEDEC Code - Weight(g)
Metal seal 42pin 600mil DIP
D
42 22
c
1
21
Symbol A A1 A2 b b1 c D E e e1 L Z
A2
Z
e
b
b1 SEATING PLANE
Dimension in Millimeters Min Nom Max 5.0 - - - - 1.0 3.44 - - 0.38 0.54 0.46 0.7 0.8 0.9 0.17 0.33 0.25 - - 41.1 - 15.8 - - - 1.778 - - 15.24 3.05 - - - - 3.05
L
A
A1
e1
E
49
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
* *
* *
*
(c) 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Mar. 2000. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 1.1 First Edition Font errors are revised.
3850 GROUP (SPEC. H) DATA SHEET
Revision Description Rev. date 000309 000322
(1/1)

▲Up To Search▲

Price & Availability of M38503M4H

	To Download M38503M4H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .